Experimental Demonstration of Optically Disaggregated Memory for Edge Data Centers

This paper shows the experimental demonstration of optically disaggregated memory. A novel system architecture based on disaggregated memory access logic and optical circuit switch is proposed. For the demonstration, optical circuit switch consisting of 9 × 9 AWGR and tunable optical transceivers was applied. The 9 × 9 AWGR has a maximum insertion loss of 3.2 dB and a latency of less than 12.8 ns over full C-band range. The disaggregated memory access logic was implemented in FPGAs. The measured round-trip time to access disaggregated memory was 934.4 ns and measured maximum data rate to read 64 bytes data from disaggregated memory was 7.352 Gbps over 10 Gbps optical link.