Reset Variability in Phase Change Memory for Hardware Security Applications

The rapid quench from melt associated with the reset operation in phase change memory is a suitable physical process to leverage programming variability for hardware security. We have experimentally characterized cell-to-cell programming variability in Ge
₂
Sb
₂
Te
₅
(GST) line cells using a single reset voltage pulse with moderate amplitude. We have observed that the cell dimensions and programming pulse parameters play a critical role on the programming variability. Cells with larger length-to-width ratios (L/W ≥ 1.8) show greater programming variability when moderate reset voltage amplitudes (V
_appl
) are applied. This variability is further increased with shorter pulse edges (t
_edge
) of the applied pulses. We have performed a study for a reset-variability-based physical unclonable function (PUF) with 85 cells (with L/W = 4) by applying identical single pulses with shorter t
_edge
and a pre-calibrated V
_appl
. Cells are randomly programmed to the full reset (high-resistance-state or HRS), or the partial reset or set (low-resistance-state or LRS) states with an equal probability and the two states are separated by ~1.5 order of magnitude. No bit flipping is observed after 9 months of programming and instead, the separation increases to ~3 orders of magnitude because of the upward and downward resistance drift of the HRS and LRS states. The underlying physical mechanisms behind the enhanced variability are identified as thermal runaway at the onset of GST melting and the additional current overshoot due to the parasitic capacitances, based on the results obtained from COMSOL finite element simulations and SPICE circuit modeling of the experimental setup.