The Impact of Hardware Features on the Processor Instruction Set Architecture

In a multi-level computer architecture, the processor instruction set architecture is the interface between hardware and software. The computer's CPU is only capable of executing machine code that uses special encoding that matches its command architecture. The article shows that using a compiler to convert source code to machine (binary) code that the processor could directly execute has its advantages. In particular, high portability of a program written with the use of a high-level language that has a compiler for the corresponding platform, which is explained by the fact that the source code is not bound to a specific processor instruction set architecture. It is shown that one and the same instruction set architecture can correspond to many implementations. Various hardware features affecting the architecture of processor commands are briefly considered: the digit capacity of numbers, bytes and machine words, the size of the processed data and registers, the number of registers, processor flags, interrupts, etc. are considered. The main I/O architectures and a number of other specific features are described which can greatly complicate binary translation of code of one architecture on another making processor architectures incompatible with each other on the semantic level.