Assessment of Linear, Hexagonal, and Octagonal Cell Topologies for 650 V 4H-SiC Inversion-Channel Planar-Gate Power JBSFETs Fabricated With 27 nm Gate Oxide Thickness

A 27 nm gate oxide thickness has been successfully used for manufacturing high performance 650V 4H-SiC planar-gate, inversion-channel power JBSFETs in a 6-inch commercial foundry with three (Linear, Hexagonal, and Octagonal) cell topologies. The 27 nm gate oxide thickness allows operation of these JBSFETs at a gate bias of 15 V compared with 20 V used in previous reports for devices with 55 nm gate oxide thickness. The width for the Schottky contact was varied to optimize the performance of the JBS diode in the third quadrant for each cell topology. An on-state voltage drop of 2.5 V or less was achieved in the third quadrant for all the cell topologies by current flow through the integrated JBS diode, satisfying the objective of effectively by-passing the MOSFET body diode. The best breakdown voltage was achieved using the Octagonal cell topology with a half-cell Schottky contact width of 1.1 μm . It had a breakdown voltage of 850 V with a low leakage current of less than 5 nA at 650 V. The Linear cell (with half-cell Schottky contact width of 1.0 μm) and the Octagonal cell (with half-cell Schottky contact width of 2.8 μm) had blocking voltages of 800 V. The hexagonal cell topology (with half-cell Schottky contact width of 1.5 μm) had the worst blocking voltage of 715 V. Numerical simulation results are provided to show that the leakage current in all cell topologies begins to increase when the electric field at the Schottky contact exceeds 1.5 MV/cm. The lowest specific on-resistance was obtained with the hexagonal cell topology but its gate-drain charge was 2× larger than the conventional Linear cell design. The Octagonal cell topology with half-cell Schottky contact width of 1.1 μm had the same specific on-resistance as the Linear cell case with 2× smaller gate-drain charge. This work demonstrates for the first time that excellent High-Frequency Figures-of-Merit can be achieved with a reduced gate drive voltage of 15 V for 650 V SiC JBSFETs by using a smaller gate oxide thickness of 27 nm and the Octagonal cell topology.