Improved High Speed Approximate Multiplier

Digital multiplication generally produces large complicated results due to its large inputs. As the applications of digital multipliers are inherently error tolerable, approximate multipliers are designed. The aim of using approximate multipliers is to reduce the size and complexity of the operation while still retaining its meaning. Compressors have a significant role in reducing the size of the intermediate or final outputs. The proposed design uses a tree compressor which contains an XOR-MUX adder. The presence of XOR-MUX adder simultaneously lessens the quantity of logic gates used and the number of inputs processed. An 8x8 multiplier design is proposed using the proposed tree compressor. This compressor reduces the delay of the multiplier by 12.6% compared to the previous multiplier which used approximate tree compressor. The accuracy is decreased by a small amount of 0.5%. Hence, this multiplier can be used for designs which require faster processing speed.