Power and Performance optimized Domino Comparator in 7nm FinFET for TLBs

Translation look aside buffers (TLB) are used to translate virtual address to physical address in microprocessors. Translation Lookaside Buffers (TLB) make use of high-speed domino-based address comparator to generate sense address mismatches faster. Domino logic circuits are used in designs to achieve higher speeds but are prone to PVT variations. In advanced FinFET nodes, higher metal resistances and capacitances limit the performance and power reduction. This paper presents the optimization of domino address comparator in 7nm technology to overcome the speed and power limitations. The banking technique used in this study compares the performance and reliability of the domino comparator based on the domino node capacitance. The proposed technique improved power and performance significantly for 128-bit and 64-bit address comparators.