High-Speed and Energy-Efficient Ring-Oscillator for Analog-to-Digital Conversion

Highly dependence of the power consumption with respect to the voltage supply makes current finer CMOS technologies become supplied with lower-than-1 V. Voltage-controlled-oscillator based analog-to-digital converters implemented with ring-oscillators scales properly with that requirement. However, conventional implementations of ring-oscillators limit the oscillation frequency due to the lack of available voltage to feed high currents. In this manuscript, we propose a novel circuit for a ring-oscillator that overcomes this issue. With only two devices between the supply nodes a delay cell is built. This allows us to reduce the voltage supply for certain oscillation requirements. In addition, the lower number of devices connected to the output nodes supposes lower parasitic capacitance and a reduction in the minimum achievable time delay, which increases the potential resolution. The proposed circuit is theoretically described and validated by simulation in a 65-nm CMOS process. Comparisons to the conventional implementations are made, showing improvements in terms of resolution, power, and area.