Design for Void Free Transfer Molding SiP

The molded underfill (MK) process for system-in-package (SiP) assembly has been widely used for recent years. In the past, the main structure of the MK was molded flip chip chip scale package (MFCCSP). Later, as the number of components increased, the mold flow became complicated, and the void issue increased, it evolved into complicated SiP. Nowadays, the metal lid SiP module is gradually moving towards the MUF SiP package market. Transfer molding for SiP is widely used in product packaging nowadays, such as mobile watch, wifi module and power management integrated circuit (PMIC) for mobile phone and portable devices, etc. The microelectronics products of SiP with more increasing challenges are faced to assure molding capability with rapid advances in flip chip technology such as surface mount technology (SMT) density, component counts become larger and number of bumps increase, especially when transfer molding process is used. There is one important challenge that faced severe air void entrapment under the die (bumps region). At present, there are mainly the following reasons leading to void issues: 1. mold thickness is too thick, 2. bump counts increase or smaller bump height, 3. mold gap smaller, 4. viscosity of epoxy molding compound (EMC) is too high. Generally, the experiments involving a lot of design of experiment (DoE) matrixes which spend a lot of time to solve air void issue. As above reasons, the mold flow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of SiP with mold thickness and mold gap design, which can reduce development cycle time before mass production. In addition, the trend of the impact on void will be discussed in the acceptable range of EMC material properties and cavity vacuum value. At present, there are several key factors that affect void issues, including component/mold volume ratio, main component size, space in end of row, side space, mold thickness and bump layout, etc. We have proposed general design guidance for low risk: mold thickness divided by minimum bump thickness index should be less than 5. If number of bumps is greater, decrease mold thickness can improve void risk issue. The results of mold flow simulation indicate that the above mentioned advanced SiP package structure design would lead to low void issue. The transfer molding mechanism and the design guidance of SiP for engineering application will be presented and discussed in this paper.