Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders

This paper designs and reports energy efficient subthreshold adders using 22 nm FDSOI technology. The dynamic body biasing technique and multi-threshold voltage devices have been used to match Pull up/Pull down networks (PUN/PDN). The post-layout simulation results show that the logic gates and full adder circuit based on dynamic body biasing are more robust than those with conventional body bias against process, voltage, and temperature (PVT) variations at ultra low supply voltages. The adder based on the conventional and dynamic body biasing techniques have achieved energy per addition of 0.23 fJ at Vdd =300 mV and 0.56 fJ at Vdd =140 mV, respectively. Compared to the other published subthreshold adders in [1] and [2], the energy per addition for our designed adders improved by 2.82X, 28.1X, respectively. The minimum operating supply voltage for dynamic and conventional body bias adders based on Monte Carlo simulations taking into account both mismatch and process variations are 140 and 200 mV, respectively. The area for conventional body biased adder has been reduced by 43.9 and 38.8 percent compared to those of the adders in [1] and [3], respectively.