Investigation on the Impact of Supply Voltage in Subthreshold Leakage Mitigation

Subthreshold leakage is the significant power squandering leakage component and boosts up the static power consumption. A novel circuit-level subthreshold leakage reduction technique, called as Short-pulse POwer Gated Approach (SPOGA) is proposed. The SPOGA substantially reduces the subthreshold leakage and provides good leakage savings at the sleep state of combinational circuits. Nevertheless, the power management of low duty cycle applications involves in the reduction of dynamic power with supply voltage scaling, which impacts the behavior of short channel transistors of the circuit. Also, the technology scaling reduces the supply voltage, which influences the short channel effects (SCE) and consequently increases the subthreshold leakage. So, the performance analysis of the SPOGA for the reduction in subthreshold leakage with changes in supply voltage is to be done. Hence, the paper aims at performing the analysis of subthreshold leakage reduction at three supply voltages: 1V, 800mV and 600mV. The logic gates and arithmetic circuits are designed using Cadence GPDK090 Virtuoso Schematic and simulation is carried out using Cadence Spectre. The SPOGA provides excellent leakage reduction with supply voltage variations and there by substantially reduces the static power consumption of the circuits.