A SAR ADC Based Time-to-Digital Converter in CMOS Technology

This paper presents an 8-bit Time-to-Digital Converter (TDC) based on Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC) architecture. The proposed multi-stage architecture converts a time interval to a voltage and then delivers it to a SAR ADC for voltage-to-time conversion. Unlike other SAR ADC architectures, this structure is not complicated and does not use a high number of capacitors. This design includes several parts like comparator and subtractor that are designed optimally. In this work, quantization noise is decreased by first-order noise shaping. The conversion rate of the proposed SAR TDC is 200 MHz, and the TDC resolution is 5ps. The proposed schema is designed and simulated in a standard .18μm CMOS technology and consumes a maximum of 6mW power from a 1.8 V supply.