An 87-dB-SNDR 1MS/s Bilateral Bootstrapped CMOS Switch for Sample-and-Hold Circuit

This paper proposes a new switch to be used in sample-and-hold circuits. Due to its structure, it is named bilateral bootstrapped CMOS switch. It consists of a CMOS switch that is bootstrapped from both sides in order to have a constant V_GS through the full swing of the input voltage and bulks of the transistors are connected such that the ON-resistance of the proposed bilateral bootstrapped CMOS switch is constant through the rail-to-rail swing of the input voltage. The proposed switch is capable of driving large capacitance loads with high linearity and high speed. The proposed circuit is designed to be used in a 14 bit 1MS/s SAR ADC (Successive Approximation Register Analog to Digital Converters). It is designed in TSMC 180nm CMOS Technology. The proposed bilateral bootstrapped CMOS switch is used in differential configuration and it is driving a total capacitance of 344pF (172pF in each side) in a sampling rate of 1MS/s. The supply voltage is 1.8V. Simulations shows that it have achieved an 87-dB SNDR (Signal to Noise and Distortion Ratio) at the sampling rate of 1MS/s.