Reliability Estimation of CNTFET-based Combinational Logic Circuits

One of the major concern about CNTFET-based logic circuit design is high fault rate. An efficient approach based on probability transfer matrix (PTM), to evaluate the reliability of such circuits has been developed in this paper. In this method, the probability of correct and incorrect states of a node are evaluated and propagated to the circuit's primary output. The accuracy of the method has been depicted comparing to the Monte Carlo method. The simulation results show less than 1% error in reliability estimation of CNTFET-based logic circuits.