Noninvasive Backside Circuit Edit Workflow using Low-kV STI Exposure

This paper describes a novel workflow for backside Circuit-Edit (CE) in which low beam energy is used to expose the Shallow Trench Isolation (STI) of a modern 7 nm process without incurring any significant effects on the device's functionality. Due to the non-destructive nature of this method for exposing STI, a much larger area can be exposed for significant improvement in FIB milling/deposition pattern placement accuracy. This helps prevent inadvertent exposure of active transistor region during the circuit edit process. Moreover, the result of exposing a larger area of STI improves Signal to Noise Ratio (SNR) by reducing the aspect ratio of the access hole necessary for reaching the buried signal of interest. In this body of work, we will explore the impact of exposing the STI of a Dynamic Ring Oscillator (DRO) structure under 30 kV and 5 kV beam energy. We will present the frequency shift associated with exposing the STI at 5 kV and compare that with results attained at 30 kV. We will explain the mechanism behind the preservation of the device functionality through TRIM simulation and TEM analysis.