A Square Wave-Based Digital Foreground Calibration Algorithm of a Pipeline ADC Using Approximate Harmonic Sampling

This brief proposes a digital foreground calibration algorithm of a pipeline ADC, using the Square wave signal as the input. The principle of equivalent radix extraction technique using approximate harmonic sampling is used to remove the ADC non-linearities. Linearity errors caused due to finite op amp gain, capacitor mismatches and effect of parasitic capacitance are eliminated by the proposed calibration technique. Two front-end stages of a 12-bit pipeline ADC are incorporated with low amplifier gain of 40 dB, capacitor mismatch of ±5 % ≤ γ ≤ ±10 %. Non-linearities arising due to these factors are calibrated and results are verified using behavioural simulation.