Accelerating 3D Vertical Resistive Memories with Opportunistic Write Latency Reduction

The 3D Vertical Resistive Memory (3D-VRAM) is emerging as a promising non-volatile memory (NVM) technology to construct large capacity main memories in future computing systems. In addition to low energy-efficiency and non-volatility, ReRAM (Resistive Memory) achieves excellent density and scalability by vertically stacking multiple layers of cross-point arrays. However, 3D-VRAM arrays have enormous amount of sneaky paths, which degrade write performance and reliability dramatically. In this paper, we propose a collection of techniques to reduce write latency in 3D-VRAM arrays. We propose an in-memory data encoding scheme to reduce the worst-case number of low resistance state (LRS) cells, a data pattern estimator for assessing cell resistance distributions, and a write time reduction scheme that opportunistically reduces RESET latency with runtime data patterns. On average, our proposed design reduces write latency by 25.98×, improves overall performance by 6.92× and reduces dynamic energy consumption by 52.4% compared to a baseline design.