Automated Synthesis of Custom Networks-on-Chip for Real World Applications

Network-on-Chip (NoC), using a packetized communication model presents a scalable interconnect infrastructure for System-on-Chip (SoC) architectures that meets its Performance, Power and Area (PPA) objectives. A typical NoC consists of building blocks such as routers, resizers and Power and Clock Domain Converters (PCDC). Hand crafting a NoC that meets PPA requirements within Time-to-Market (TTM) constraints is difficult if not intractable for real world systems. In this paper, we present an automated NoC synthesis tool that generates PPA optimized, customized NoC for any system from its behavioral specification. The tool provides solution based on multiple isolated communicating trees with fixed points of inter-communication amongst them. It models a variety of requirements like deadlock-avoidance, quality of service etc. as conflicts represented in a Traffic Conflict Graph (TCG) and uses combinatorial optimization techniques to minimize the conflicts resulting in a better overall design. This is in contrast with traditional approaches which focus only on reducing communication overheads. Implementation and evaluation of the tool in production-grade designs shows that it achieves better topologies as compared to hand-crafted NoCs in only a fraction of time. Across several multi-million gate SoCs, the tool has reduced latency, buffer-size and area by 40%, 50% and 8% on average respectively w.r.t hand-crafted NoCs, while meeting user-specified performance requirements. Use of this tool has brought down the typical NoC design time from several months to less than two weeks thereby considerably reducing design effort and TTM targets.