Dual-Output LUT Merging during FPGA Technology Mapping

Modern commercial Field-Programmable Gate Array (FPGA) architectures support dual-output look-up tables (LUTs). If the number of total inputs in two small LUTs do not exceed the constraint, e.g., 5 in Xilinx UltraScale+ series, we can pack them into one dual-output LUT to reduce area, i.e., the number of LUTs. However, previous works have not fully utilized this feature. They usually generate single-output LUTs in the technology mapping phase and merge LUTs in a later packing phase. In this situation, they cannot get LUT merging information during technology mapping and will generate some single-output LUTs that are not suitable for merging. In this work, we directly generate dual-output LUTs in the technology mapping phase and propose a novel cut-based mapping flow. The mapping flow consists of several mapping passes with different cut selection metrics. In each pass, we first compute the priority single-output cuts of each node. Then, we merge dual-output cuts from the priority cuts to generate a mapped LUT netlist. Finally, we do some local refinement to further improve the merging rate and reduce area. Experimental evaluation shows that our mapping flow can merge up to 14.89% more LUTs and save up to 13.98% area on average, compared to the state-of-the-art technology mapping tool ABC, without worsening the total delay.