Retiming for High-performance Superconductive Circuits with Register Energy Minimization

Retiming, which is a circuit transformation whereby registers are relocated to optimize performance, area, or energy consumption, has reached a high level of maturity in CMOS designs. However, the recent emergence and rapid rise of non-CMOS technologies are introducing new and important variants of the standard retiming problems. This paper presents a path-balancing retiming transformation, taking superconductive designs as an evaluation case study, where the retiming solution must achieve full path balancing of the circuit while simultaneously minimizing the energy consumption of inserted registers with performance constraints. This optimization problem, which is called a constrained register energy minimization (CREM) problem, is precisely formulated and polynomially solved. Next, the CREM problem formulation is extended to retime the circuit under a dual clocking architecture requiring partially (bounded depth difference) path balanced (PPB) characteristics only. It is shown that the PPB-CREM problem is NP-complete. We thus propose a polynomial-time approximation algorithm with a bounded error to solve this retiming variant. Compared to prior work, our approach reduces 38% of register count and 50% of register energy consumption of 14 benchmark circuits on average. Moreover, the competitive ratio of the register energy consumption between our approximate solution and the optimal solution is on average only 1.08.