Meshed Stack Via Design Considering Complicated Design Rules with Automatic Constraint Generation

In advanced semiconductor processes, the dramatic shrink of layout features has made a significant impact on circuit delay and electromigration (EM). Recently, meshed stack vias (MSVs) have been proposed as a solution to improve circuit timing and signal integrity, each of which is a multi-layer mesh structure composed of parallel metal shapes and vias. Due to the introduced MSV rules and more and more complicated design rules, MSV design becomes a very challenging problem, while no previous work has addressed this issue. In this paper, we propose the first work of MSV design by developing two different methods: an integer linear programming (ILP)-based and a dynamic programming (DP)-based methods. Unlike most previous works devoting themselves to formulating sophisticated constraints for each complicated design rule, we propose an automatic constraint generation (ACG) framework to iteratively resolve design rule violations (DRVs) without any effort in understanding all design rules, which contributes to a general MSV design methodology applicable to different technology nodes. Experimental results show that both the ILP-based and DP-based approaches can averagely achieve 92% MSV insertion rate for a set of industrial benchmarks. In addition, by adopting the proposed ACG framework, 100% MSV insertion rate can be achieved without causing any DRV.