Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth Variations

The sensing system in NAND flash memories is a complex mixed-signal circuit consisting of a large-scale cell array, wordline decoders, page buffers, analog/digital bit-counters, and digital sequence controllers. This paper proposes a model and simulation framework that can assess the effectiveness of various incremental/adaptive algorithms used by digital controllers for the read, program, and erase operations, while simulating the progression of individual cell threshold voltages (V
_th
) and modeling the detailed analog characteristics of the page buffers. The proposed model is written entirely in SystemVerilog, and its analog parts are described using the XMODEL primitives, which enable efficient and event-driven simulation of analog circuits. The proposed model can simulate a 40μs-long incremental step pulse programming (ISPP) sequence with the maximum loop iteration count of 4 on a 12K-bit block of single-level cells (SLC) in less than 2 minutes, and can assess the trade-offs between the programming speed and reliability as a function of the pulse step size and the impacts of the page buffer's sensing time on the final cell V
_th
distribution.