An Algorithm for Rule-based Layout Pattern Matching

As feature size continues to shrink and design complexity continues to increase, a circuit layout has become more difficult to verify than before. Rule-based pattern matching is considered as a practical approach for layout verification, but unlike traditional ones, this paper focuses on three kinds of rules and presents an efficient pattern matching algorithm. Given a layout and a set of rules, our algorithm first adopts a line sweep method to scan the layout twice such that for each given rule, it collects all pairs of polygons satisfying that rule. It then bases on the collected polygon pairs to find all layout patterns each of which meets the given set of all rules. Experimental results show that our algorithm is able to find the correct set of matched patterns efficiently for each test case.