Raising the Abstraction Level of a Deep Learning Design on FPGAs

Autonomous and intelligent systems based on deep learning, continuously attract the attention of researchers and engineers. With the progress on the application of deep learning for modern applications arises the challenge of reaching real-time processing. To face this challenge, Field Programmable Gate Arrays (FPGAs) can be used; however, deep learning generic implementations on an FPGA are still a topic of research. Advances in FPGA technology allow for designs based on High-Level Synthesis (HLS) for accelerating and facilitating implementations of complex problems on hardware. A platform based on HLS for emulating a generic parameterizable deep learning system on an FPGA is proposed in this paper, allowing for the implementation of any structure based on the following layers: convolution, max-pooling, batch-normalization, and fully connected networks. Through this platform, it is possible to implement a deep learning system on FPGAs using an N-Fold or a Flow architecture without the assistance of central processing units. Whereas the N-Fold architecture requires fewer hardware resources, as it re-uses resources, the Flow architecture presents a higher throughput. The developed platform improves the deep learning design productivity by automating the generation of the system, achieving efficiency and raising the level of abstraction, as was experimentally verified and evaluated.