A parallel real time implementation of stereo matching

We present a VLSI architecture and implementation for a highly parallel trellis-based stereo matching algorithm that has been previously presented by the authors. The algorithm obtains disparity (depth) information from a pair of images and has a complexity of O(N/sup 2/) for N pixel scan lines and O(N) operations can be performed in parallel. The architecture consists of a linear array of identical processing elements with only nearest-neighbor communication. The host provides pixel data to each end of the array during the forward iterations and reads the computed disparity during the backward iterations. The design is highly scalable. A 10 processor array that can handle 340 pixel scan lines has been fabricated using a 0.65 /spl mu/m CMOS process and has achieved 8 Mpixels/s throughput.