VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay Models

In the advanced technology nodes, process parameter variations are increasingly resulting in unpredictable device behavior. The issue is even aggravated by low power requirements which stretches the transistor operation into near-threshold regime. Despite device simulation gives precise results, it is time-consuming for static timing analysis and dynamic timing analysis. In this paper, we propose VASTA, a statistical timing analysis tool based on the variation-aware standard cell library. The tool efficiently supports statistical static timing analysis (SSTA) and statistical dynamic timing analysis (SDTA). The standard cell library models delay under operating environment effects by using quadratic regressions and multivariate adaptive regression splines. VASTA works on industry formats (.v and.sdc) and is designed to run in parallel during both SSTA and SDTA. The statistical cell library is built and verified using SMIC 40 nm and 28 nm PDK. The mean and standard deviation errors of cell delay models are 2.77% and 1.68% compared with SPICE simulation results under 10k Monte Carlo samples. The SSTA and SDTA are tested with ISCAS85, ISCAS89, and EPFL benchmark suites. The average mean and standard deviation errors of SSTA are 4.01% and 2.03%, which are similar to SDTA. Meanwhile, our SDTA is 17.7 times faster than traditional corner-based dynamic timing analysis which relies on generating .vcd cell activity files.