Sub Threshold Conduction and the Possible Approach Towards Low Power Design using Bootstrapping Technique: A Prototype Design

The main objective of this paper is to provide sub-threshold conduction and optimal low power design for very large-scale integration (VLSI) designer. The work mainly focuses on low power and sub-threshold conduction allowing circuit to operate below its rated voltage. The problem arises due to continuous scaling of elements at different levels as was set by ITRS recommendation. Various techniques at different level had been proposed in order to overcome the drawback to a greater extent. Furthermore the no. of gate per chip has increased, rise in operating frequency and many more has resulted in greater power dissipation. The demand on low power ICs is also increasing each year. Following Moore's law, semiconductor industries are challenged every two years to scale down CMOS technology, enabling high integration, high speed and low-cost chips due to the small die areas. When we go for scaling with some parameter (say K=.7), various changes have been found and the main focus is towards low leakage current reduction and the circuit operation below threshold region of devices.