Evaluation of tests to examine charging damage in ion implantation and plasma processes: using controlled stress environments

Charging damage is a critical issue in both plasma processing and ion implantation systems. Charging damage is typically studied with one of several distinct types of test structures. One of the more common is an "antenna" MOS capacitor test structure. After the device is subjected to the charging environment, plasma or implantation, the gate dielectric is then analyzed for damage. For this paper, we will present detailed results from three analysis techniques on various dielectrics. The analysis techniques employed in this study are: measurement of temporal change in induced voltage at a low current density (dV/dt); measurement of induced leakage current at a low voltage (/spl sim/2 V); and measurement of induced voltage at a high, stressing, current density (/spl sim/1 A/cm/sup 2/) Damage to the dielectric was induced with a controlled damage current, of known length and strength. Dielectrics ranged from 100 /spl Aring/ oxide to sub-40 /spl Aring/ nitrided oxides. The purpose of this work is to determine the most appropriate technique for characterizing plasma or ion implantation charging dielectric degradation in the ultra-thin dielectric regime, as well as to gain a baseline understanding of the damage under controlled conditions. Preliminary examination of the data indicates that each of these techniques gives the same results. It is envisioned that the results of this study can be used as a gauge for future experiments, as well as to provide an estimate of the damage currents in actual ion implantation and plasma processing environments.