Influence of scribe lanes on wafer potentials and charging damage

Experimental results show that scribe lane structures can exert a significant influence on surface-substrate potentials and J-V characteristics measured on a wafer in ion-implant processes. This suggests that scribe lane structures used for process control in IC manufacturing, as well as the internal layout of the product itself, may exert significant influence on the surface-to-substrate potentials observed within a die during IC processing, thereby increasing or decreasing the likelihood of device damage.