Predictive Compact Modeling of Abnormal LDMOS Characteristics Due to Overlap-Length Modification

Further compact-model development for LDMOS is reported, enabling concurrent device and circuit optimizations by only varying the ratio between gate-overlap length (L
_over
) and resistive-drift length (L
_drift
). Different from the conventional carrier-dynamics understanding within these two regions, LDMOS shows abnormal characteristics during such a ratio variation. The pinch-off condition occurs under the gate overlap region, and the pinch-off point is found to move along Lover with increased drain voltage, even under the accumulation condition. This means that carrier conductivity is no longer controlled by the gate voltage but by the drain voltage. The precise pinch-off condition is determined by the field balancing within gate-overlap and resistive-drift regions. The pinch-off length (ΔL) within Lover sustains V
_ds
together with L
_drift
. Thus, the pinch-off region contributes as a part of Ldrift and improves the device's high-voltage applicability. A new model is developed to describe this balancing phenomenon analytically, where the key physical quantity is ΔL. The developed ΔL model considers the potential distribution along Lover together with L
_drift
. At the pinch-off point, the field induced by V
_gs
and that by V
_ds
are assumed to be equal, which derives an analytical description for ΔL. Evaluation results with the developed model are verified with 2D-numerical-device-simulation results.