A Novel Ultralow RON,sp Triple RESURF LDMOS With Sandwich n-p-n Layer

This article proposes a novel ultralow specific ON-resistance (
${R}_{ \mathrm{\scriptscriptstyle {ON},sp}}$
) triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with sandwich n-p-n layer. Compared with the conventional triple RESURF LDMOS with n-type top layer (NTTR LDMOS), the new structure is characterized by an additional N-buried layer below the P-buried layer. Due to the introduction of N-buried layer, the concentration of N-top layer will decrease to ensure charge balance, thus making the surface electric field distribution better and the higher additional doping introduced by N-top and N-buried layers can be achieved. The dose and implantation energy of n-p-n layers were simulated and optimized. Furthermore, in order to eliminate the premature avalanche breakdown occurring in the source-centered termination region, substrate termination technology (STT) is applied to avoid the high electric field peaks generated in the curved source region with small curvature radius. But the use of STT makes it easy to breakdown in the transitional region compared with the straight region. Therefore, the transitional region is studied and the crucial parameter
$\Delta {L}$
in the layout of transitional region is also optimized. The fabricated device experimentally demonstrated improved performance with low
${R}_{ \mathrm{\scriptscriptstyle {ON},sp}}$
of 78.3
$\text{m}\Omega \cdot $
cm
²
and high breakdown voltage (BV) of 795 V, and the experimental
${R}_{ \mathrm{\scriptscriptstyle {ON},sp}}$
is 26.8% lower than that of the conventional triple RESURF LDMOS (CTR LDMOS) and 10% lower than that of the NTTR LDMOS based on
${L}_{d} = 67 \mu \text{m}$
, which can break the silicon limit of CTR and NTTR LDMOS and meet the demand of 700-V high-voltage integrated circuit applications.