Challenges and solutions in the process integration of ultra-shallow junctions in advanced CMOS technology

The formation of ultra-shallow junctions with low sheet resistance poses a major challenge in the scaling of advanced CMOS devices. Optimal device characteristics are achieved by a combination of low energy implants with low thermal budget activation. In this paper, the role of various thermal processes such as extension and source/drain anneal and deposition of nitrides and oxides on controlling junction parameters are examined. In addition, the effect of anneal ambient in the presence of an ultra-thin oxide layer is examined. Effect of junction profiles on device performance of a 150 nm CMOS is also reported. Improved transistor performance is obtained by minimizing thermal budget and optimizing the implanted extension dose.