Junction capacitance reduction by S/D junction compensation implant

Parasitic capacitances normally present in CMOS transistors are recognized as detrimental factors in overall Transistor and Circuit performance. In this report results from an investigation of a simple method to reduce Junction Capacitance (Cj) in 0.20 and 0.17 /spl mu/m embedded DRAM technologies are presented. The results shown indicate that Cj of both NFETs and PFETs can be reduced (without significantly affecting other transistor parameters) by about 20%.