SiGe device architectures synthesised by local area Ge/sup +/ implantation-structural and electrical characterisation

SiGe device islands have been synthesised by Ge+ ion implantation of doses of 0.45/spl times/10/sup 16/Ge/sup +//cm to 4.05/spl times/10/sup 16/Ge/sup +//cm/sup 2/ at 100 keV or 200 keV into patterned [100] bulk silicon wafers. The control of 'mask edge defects ' and 'end of range ' defects has been achieved by applying Si/sup +/ post-amorphisation, where the ions are implanted into a wider window, and by using solid phase epitaxial regrowth. Defect free SiGe alloy islands with a peak Ge concentration of /spl sim/6 at% and minority carrier generation lifetimes comparable to bulk silicon (/spl sim//spl mu/s) have been successfully produced. The integration of this synthesis process into CMOS and bipolar technologies is discussed. Realization of shallower islands, with dimensions more consistent with future generations of advanced devices and with higher Ge contents, is in hand.