A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications

This article proposes reconfigurable maximum a posteriori (MAP) decoding algorithm which operates in multiple radix modes to hard decode the information bits with variable throughput by consuming constant power. Subsequently, a new digital decoder-architecture for this MAP decoding algorithm has been designed that operates in radix-2/4/8 modes. Furthermore, reconfigurable microarchitectures of state-metric and logarithmic-likelihood-ratio (LLR) computation units are presented in this article. Performance analyses of the proposed algorithm have been performed in additive-white Gaussiannoise (AWGN) channel environment where it achieved a biterror-rate (BER) of 10
^-4
at a signal-to-noise ratio (SNR) of 5 dB. Suggested multiple-radix MAP-decoder is fabricated in united-microelectronics-corporation (UMC) 130-nm-CMOS technology node and it occupies die and core areas of 2.35 and 1.28 mm
²
, respectively, operating at a maximum clock frequency of 204 MHz. This MAP decoder ASIC-chip delivers throughputs of 201, 403, and 605 Mb/s while operating in radix-2, 4 and 8 modes, respectively, consuming a total power of 92 mW. Our chip achieves 0.15 nJ/bit of energy efficiency, which is 30% better than the most energy-efficient implementation from literature. Likewise, it delivers 39% higher throughput and 70× better area-efficiency than the state-of-the-art work.