Bridging Gaps in Paper Design Considering Impacts of Switching Speed and Power-loop Layout

In power electronics design, the selection of power semiconductors mainly considers the voltage and current ratings, power loss, and operating frequency capability. However, in the paper design stage, the impacts of switching speed and busbar or PCB layouts related geometries design on the converter system are not considered comprehensively, which may introduce a trial-and-error procedure of selecting the gate resistance in the implementations due to overvoltage and cooling capability issues. To shrink the design gaps between the paper design and implementations, with advanced modeling methods and design automation programs, this paper proposes a systematic design approach for power semiconductors selection and cooling system design considering the impacts of switching speed and power-loop layout. The discrete-time switching behavior model for the switching speed prediction and automatic geometry creation program for the power-loop layout are developed to determine the gate resistance in the paper design stage, and the partial element equivalent circuits (PEEC) numerical modeling method is adopted to extract the parasitic inductance for the created geometries. After the determination of gate resistances for the selected device and topology, a multi-variable switching loss scaling method with the discrete-time switching behavior model is used to get the more accurate device losses for the cooling design. A complete design iteration and related verifications are also given in this paper.