A traffic control mechanism based on the load of output ports in an ATM switch

In this paper, we propose a traffic control mechanism for ATM switches consisting of common buffered switch fabrics without buffer separation. The proposed mechanism allocates the rate of incoming traffic into switch fabrics according to the load of output ports. In the method, an egress line interface module (LIM) computes the available bandwidth (ABW) for each connection of non-real time traffic based on the load of the output port. The egress LIM sends back the ABW to ingress LIMs for each connection. According to the ABW, the ingress LIMs schedule the incoming traffic into switch fabrics of each connection. We also propose a rate-based cell-scheduling algorithm for the proposed mechanism. The proposed mechanism has been implemented by using FPGAs in the ACE256 ATM switch.