Design Automation and Implementation of Machine Learning Classifier Chips

This paper presents a novel framework that automates the creation of a trained-classifier integrated circuit from a dataset. The framework accepts a dataset in a comma-separated value format and performs several processing steps to create a trained model. After creating the model, the framework generates a tree-based machine learning classifier in two formats; Extensible Markup Language (XML) and Verilog. We use the XML representation to present the hierarchy of the generated tree and the Verilog code as a hardware description language representation of the trained model. Our framework uses the Verilog code as an input to a Field programmable Gate Array (FPGA) design validation flow. Then, we automate the Application Specific Integrated Circuit (ASIC) flow implementation and build a customized classifier integrated circuit. The novelty of the proposed framework lies in bridging the gap between machine learning model training and its hardware design when dealing with machine learning classifier's implementation. Our framework addresses several challenges related to the design automation and implementation of customized machine learning classifier chips from raw dataset files. We discuss these challenges in detail in this paper and explain how researchers can use our proposed framework to build low-cost, high-performance classifier chips. Our framework operates at 100 MHZ and achieves 80.79% average 10-fold cross-validation accuracy across five different datasets.