A process and technology-tolerant I/sub DDQ/ method for IC diagnosis

The use of I/sub DDQ/ test as a defect reliability screen has been widely used to improve device quality. However, the increase in subthreshold leakage currents in deep submicron technologies has made it difficult to set an absolute pass/fail threshold. Recent work has focused on strategies that calibrate for process and/or technology-related variation effects. In this paper, a new I/sub DDQ/ technique is proposed that is based on an extension of a V/sub DDT/-based method called Transient Signal Analysis (TSA). The method, called Quiescent Signal Analysis or QSA, uses the I/sub DDQ/s measured at multiple supply pins as a means of localizing defects. Increases in I/sub DDQ/ due to a defect are regionalized by the resistive element of the supply grid. Therefore, each supply pin sources a unique fraction of the total I/sub DDQ/ drawn by the defect. The method analyzes the regional I/sub DDQ/s and "triangulates" the position of the defect to an (x,y) location in the layout. This information can be used in combination with fault dictionary-based techniques as a means of further resolving the defect's location.