A Dedicated Greedy Short Path Padding Solution Method for Error Resilient Circuit Designs

Resilient circuits represent promising approaches for improving both circuit performance and tolerance for dynamic variations. However, the short path padding problem becomes severe during the implementation, resulting in significant area overhead and even frequency degradation, which might nullify the benefits of resilience. The present work addresses this issue by proposing a progressive resilient design methodology, including a clock period prediction method that can accurately access the minimum clock period possible in an early stage and a short path padding method, based on the greedy heuristic algorithm to reduce both the total padding delay and the runtime. The runtime for the padding stage is further minimized by introducing an accelerated padding method that decreases the number of point visits required during the greedy padding process. The proposed methodology is applied to several benchmark circuits, decreasing averagely 26.1% in the total number of padding buffers and 38.1% in the runtime, compared to a present state of the art methodology. Thus, this proposal not only avoids iterations of padding assignments by early period prediction, but also is a feasible and effective short path padding methodology for resilient circuits.