Implementing a Comprehensive Networks-on-Chip Generator with Optimal Configurations

Networks-on-Chip has become the de facto design paradigm for many-core systems. This poster presents a general purpose Networks-on-Chip (NoC) generator with optimal configurations, named EAGEN. The NoC producer module of EAGEN is written in Chisel3 language which generates both Verilog and C++ model for hardware implementation and software simulation, respectively. Once the application specification and design constrains are fed to EAGEN, the synthesizable RTL code with optimal configuration will be output.