Advanced 2D latch-up device simulation-a powerful tool during development in the pre-silicon phase

The consideration of parasitic effects like the ESD and latch-up sensitivity of a new technology in the early development phase is not yet established. Calibrated 2D simulation can be used for optimizing the technology according to these parasitic effects yielding to an area optimized protection concept and thus offering the possibility to reduce chip costs. In this paper, we present a 2D latch-up device simulation developed for use in the pre-silicon phase to get an optimized pre-silicon latch-up concept for Infineon's 0.13 /spl mu/m technology. Silicon verification shows the excellent simulation quality.