Nanoscale Transistor Variability Modeling: How Simple Physics Enables a Powerful Prediction Platform

Process-induced variation (PIV) is the major bottleneck for using advanced CMOS technology efficiently. Even though the multigate nature of the fin field effect transistor (FinFET), nano-wire FET (NWFET), and nanosheet FET (NSFET) make the device robust toward the short channel effects (SCEs), unpredictable device-to-device variation caused by unwanted PIV remains a challenge for the designers. In this article, we propose a generic variability model to describe the impact of PIV on performance parameters of advanced devices. The major focus of this article is to demonstrate two independent analytical models capturing the impact of metal gate granularity (MGG) and line edge roughness (LER) on the threshold voltage (<;i>V<;/i>
_{<;italic>T<;/italic>}
) of FinFET. The proposed model is not only limited to the variability estimation of <;i>V<;/i>
_{<;italic>T<;/italic>}
, but also capable of estimating the on-current (<;i>I<;/i>
_on
), subthreshold slope (SS), and off-current (<;i>I<;/i>
_off
) distribution due to LER accurately. Both the models are generic enough to be extended to be used for NWFET, and NSFET, and utilizes simple physics and mathematics, therefore, it can be implemented in any platform. The models are 100-1,000 times faster in comparison to the technology CAD (TCAD) simulations, and accuracy is on par with the TCAD results. Such models, when integrated with the existing nominal SPICE setup, the circuit-level performance prediction will be comparable to the experimental results. As the models take process-generated variations as an input to produce corresponding performance variation, it will further enable the co-optimization of the process as well as the circuit performance.