A study on the performance, complexity tradeoffs of block turbo decoder design

In this paper, results from a study of the tradeoffs between VLSI implementation complexity and performance of block turbo decoder are presented. Specifically, we address low complexity design strategies on choosing the scaling factor of the log extrinsic information, reducing the number of hard decision decodings and reducing the complexity of general hard-decision BCH decoders when soft-decision decodings are utilized.