Hardware-Efficient Emulation of Leaky Integrate-and-Fire Model Using Template-Scaling-Based Exponential Function Approximation

We present a method to emulate a leaky integrate-and-fire (LIF) model in a field-programmable gate array (FPGA) in a hardware-efficient manner. The simplified spike-response model (SRM
₀
) is chosen as an LIF model. For the hardware-efficient implementation of SRM
₀
, we adopt the template-scaling-based exponential function approximation (TS-EFA). This method allows high precision and low latency exponential function approximations with the efficient use of hardware resources. We subsequently propose an algorithm for SRM
₀
, which leverages the advantage of TS-EFA. An implementation of 512 neurons conforming to SRM
₀
in an FPGA highlights (i) high precision of SRM
₀
emulation (mean squared error of membrane potential approximation: 4×10
^-12
- 1×10
^-10
), (ii) low latency (eight clock cycles), and (iii) high efficiency in hardware usage (only 125b memory per neuron).