A pipeline 15-b 10-Msample/s analog-to-digital converter for ADSL applications

This paper describes a pipeline 15-b 10 Ms/s analog-to-digital converter in a 0.35 /spl mu/m digital CMOS technology, suitable for ADSL applications. The architecture is based on a 5.5-bit front-end stage with a current-steering DAC and a continuous-time residue amplification followed by a 10-bit conventional pipeline backend ADC. The linearity is determined by the matching accuracy of the unit current sources, which can be controlled by the area and overdrive voltage of transistors. At Nyquist sampling (5 MHz) the signal-to-noise-and-distortion (SNDR) is 78.6 dB. The ADC has a differential input rang of 1.1 V and dissipates 320 mW from a 3.3 V power supply.