Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power Optimization

Technology mapping is the key link between technology independent logic synthesis and technology dependent physical design of IC design flow. Conventionally, physical design honors the circuit structure generated by logic synthesis and then performs optimizations to meet the design requirement by using the same cell library as logic synthesis. Thus, the quality of technology mapping is bounded by the variety of library cells. To enhance the flexibility and capability, we propose an analytical mega cell methodology, which clusters the same type or different types of cells together to improve area and power. We analyze the placement of a design and rank mergeable cells for mega cell creation. Through sharing layout space or gate reduction, our approach minimizes the area and power without timing degradation. Our experiments are conducted on five types of SHA256 cores (block chain mining machines) with below 10nm process. Compared with the conventional technology mapping approach (widely adopted by commercial tools), our approach can save average 2.23% area and 14.44% total power consumption. Our results show that the proposed mega cell methodology is promising for energy and area reduction in modern block chain designs and can be easily ported to other ASIC designs.