A Sub-10fs FOM, 5000x Load Driving Capacity and 5mV Output Ripple Digital LDO with Dual-Mode Nonlinear Voltage Detector and Dead-Zone Charge Pump Loop

This paper describes an analog-assisted digital low dropout regulator (LDO) with dual-mode operation by employing a dual-mode nonlinear voltage detector (DNVD) and a charge pump (CP) LDO for enhanced transient performance and reduced output ripple. In the transient mode, the proposed digital LDO achieves a high loop gain, operating like a flash-ADC digital LDO with a nonlinear decoder. The loop gain of the digital LDO is further boosted by the CP LDO. In the steady mode, the CP LDO is turned off, and the digital LDO becomes a shift register (S/R) digital LDO with a voltage dead-zone for small output ripple. An exponential-ratio array (ERA) is designed to substantially increase the load driving capacity of power transistors. The proposed digital LDO implemented in 65nm CMOS achieves 8.69fs FOM with 5000× load driving capacity when the input voltage and the output voltage are 0.6V and 0.5V respectively. Thanks to the DNVD with the dead-zone operation, the output ripple is reduced from 20mV to 5mV, while achieving the quiescent current of 28.5μA in the steady mode.