Implementation of modified Dual-CLCG Method for Pseudorandom bit Generation

Linear Congruential Generator is the popular and most used algorithm for generating the pseudorandom number. The “Modified dual-CLCG” method, said to be secure pseudorandom bit sequence(PRBG) among the various available LFSR, LCG, Dual CLCG that generates a pseudorandom bit sequence at a periodic interval. It depends on the inequality equations to generate a pseudorandom bit sequence at a regular clock cycle with minimum hardware. This method has been developed using different parallel prefix adder based Modified dual CLCG, and the comparison is done for area and delay. This proposed method has been implemented successfully using Verilog-HDL with means of Xilinx ISE (14.7) design suite. For the physical implementation results of Linear Congruential Generator have been done using Spartan 3E. This method is mainly used in the domain of hardware security and also IOT enabled devices.