Signal Integrity Evaluation for Automotive ECU with PCIe Gen 3.0 Interface

Signal Integrity analysis forms an integral part of high speed design circuits. With complex high speed connectors and via models that are potentially degrading the signal quality in such designs, where pre layout and mainly post layout simulations help to improve the quality of critical signals. End to End circuit simulation using IBIS AMI models including S parameter model of the connector for a single lane PCIe channel Gen 3.0 and the package model of the HSIF board is performed using Ansys tool and ADS to make certain that the channel meets the PCIe SIG specifications and the results are well within the BER limits. Time Domain Reflectometry (TDR) analysis is carried out to determine impedance variations. The post layout simulations help reduce the time to market the actual high speed interface boards. It helps ensure that the designed board meets the industrial Electromagnetic Compatibility and Electromagnetic Interference testing standards in addition to automotive safety standards.