Performance analysis: D-Latch modules designed using 18nm FinFET Technology

In general, a latch also known as level triggered device is used to store single bit information. Also, the latch is considered as a building block for sequential circuits. The basic working of D-Latch is that, the input data will be transferred to the output node whenever the clock or enable signal is high. In this paper, various efficient designs of d-latch using 18nm FinFET technology are proposed. The designing of latches are very flexible when compared with flip flops. FinFET technology has many advantages over planar CMOS such as lower leakage current and lower power consumption. The circuits are designed and simulated using FinFET spectral models in Cadence virtuoso tool. The proposed latches using FinFET consumes less power and has low power delay product when compared to traditional D-Latch designs.